Effects of Heterostructure Design on Performance for Low Voltage GaN Power HEMTs. (21st February 2019)

• Record Type: Journal Article
• Authors: Binder, Andrew; Khan, Sakeenah; Yang, Wen; Yuan, Jiann-Shiun; Krishnan, Balakrishnan; Shea, Patrick M.
• Is Part Of: ECS journal of solid state science and technology. Volume 8:Number 2(2019)
• Page Start: Q15
• Page End: Q23
• Publication Date: 2019-02-21
• Subjects: Electron Devices - III-V -- Microelectronics -- Semiconductors - III-V -- fabless design -- GaN HEMT -- heterostructure layer optimization; Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2.0141902jss
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : This paper presents a fabless design approach focusing on the impact of heterostructure design on the performance of low voltage GaN power HEMTs. Compared to the standard high voltage design process, low voltage design (<100 V) comes with a unique set of challenges especially concerning breakdown rules. Low voltage simulations reveal less dependence on vertical leakage current and substrate breakdown compared to high voltage designs, and more reliance on buffer leakage and punch-through as the dominant factors leading to breakdown. To analyze the impact of heterostructure design on the device performance, optimization curves are presented for breakdown voltage, on-state resistance, and gate charge. Simulations are performed in Sentaurus TCAD and correlated to known existing experimental results where possible. Trends are presented for the optimization of the channel layer thickness, barrier layer thickness and molar fraction, and impact of an AlN interlayer.