Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration. (12th July 2019)

• Record Type: Journal Article
• Authors: Porret, C.; Hikavyy, A.; Granados, J. F. Gomez; Baudot, S.; Vohra, A.; Kunert, B.; Douhard, B.; Bogdanowicz, J.; Schaekers, M.; Kohen, D.; Margetis, J.; Tolle, J.; Lima, L. P. B.; Sammak, A.; Scappucci, G.; Rosseel, E.; Langer, R.; Loo, R.
• Is Part Of: ECS journal of solid state science and technology. Volume 8:Number 8(2019)
• Page Start: P392
• Page End: P399
• Publication Date: 2019-07-12
• Subjects: Microelectronics - Semiconductor Materials -- Low Temperature Epitaxy -- Source/Drain materials -- Strained Channels; Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2.0071908jss
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.