Optimization of Etch Process for Ultra-Narrow Via in 3D NAND Flash Memory by DOE Method. (4th December 2019)

• Record Type: Journal Article
• Authors: Ma, Haodong; Yin, Zhiping; Liu, Jun; Zheng, Biao; Wang, Fan; Xiao, Jinhua; Zheng, Zuhui; Meng, Jieyun; Luo, Jun
• Is Part Of: ECS journal of solid state science and technology. Volume 8:Number 12(2019)
• Page Start: P775
• Page End: P786
• Publication Date: 2019-12-04
• Subjects: Etching -- Microelectronics - Semiconductor Processing -- design of experiment -- dry etch -- process model; Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2.0171912jss
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : With the increase of storage density in three-dimensional NAND flash memory, technical challenges become more and more severe. Specifically, the etch process of ultra-narrow via is one of the most intricate technical challenges. The critical dimension (CD) of ultra-narrow via is sensitively affected by this process. In this paper, a Design of Experiment (DOE) was presented to develop an optimized etch process. Various statistical correlations between factors and measured results were analyzed by statistical software. Tail phenomenon and cliff effect were explicated by wafer level analysis. A process regression model was employed for process window check and process optimization. Based on data analysis, modeling, and supplementary experiments, the ratio of Cx Fy to Cx Hy Fz during the etching of anti-reflective coating (ARC) was identified as the most significant factor for the etch process of ultra-narrow via. DOE method is also helpful in developing advanced etch process in state-of-the-art 3D NAND flash memory.