Deep Level Assessment of n-Type Si/SiO2 Metal-Oxide-Semiconductor Capacitors with Embedded Ge Quantum Dots. (5th January 2018)

• Record Type: Journal Article
• Authors: Aouassa, M.; Vrielinck, H.; Simoen, E.
• Is Part Of: ECS journal of solid state science and technology. Volume 7:Number 2(2018)
• Page Start: P24
• Page End: P28
• Publication Date: 2018-01-05
• Subjects: DLTS -- Ge quantum dots -- interface states; Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2.0031802jss
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : This paper reports on a Deep-Level Transient Spectroscopy (DLTS) study of n-type silicon Metal-Oxide-Semiconductor capacitors with Ge Quantum Dots (QDs) embedded in a SiO2 gate dielectric. For a zero-dot reference and in capacitors fabricated with a 1, 2 or 3 nm amorphous Ge layer similar spectra have been obtained. They are characterized by a peak at or above room temperature for a bias pulse in depletion and by an electron trap around 200 K, which is shown to be associated with dangling bond acceptor states at the Si/SiO2 interface. The maximum density of states increases with average Ge QD size, while the average activation energy, corresponding with the peak maximum position shifts to lower values. Although no direct evidence of electron tunneling to the Ge QDs has been found so far, there is a marked impact of their presence on the Capacitance-Voltage characteristics, resulting in an increase in the accumulation capacitance with QD size, a shift of the flatband voltage toward more positive gate bias and a counterclockwise hysteresis, associated with the charging and discharging of QD levels and related Ge traps in the SiO2 .