Process Variability for Devices at and beyond the 7 nm Node. (17th October 2018)

• Record Type: Journal Article
• Authors: Lorenz, J. K.; Asenov, A.; Baer, E.; Barraud, S.; Kluepfel, F.; Millar, C.; Nedjalkov, M.
• Is Part Of: ECS journal of solid state science and technology. Volume 7:Number 11(2018)
• Page Start: P595
• Page End: P601
• Publication Date: 2018-10-17
• Subjects: Electron Devices - Silicon -- CMOS transistors -- Compact models -- Process variations; Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2.0051811jss
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : Advanced CMOS devices are increasingly affected by various kinds of process variations. Whereas the impact of statistical process variations such as Random Dopant Fluctuations has for several years been discussed in numerous publications, the effect of systematic process variations which result from non-idealities of the equipment used or from various layout issues has got much less attention. Therefore, in the first part of this paper, an overview of the sources of process variability is given. In order to assess and minimize the impact of variations on device and circuit performance, relevant systematic and statistical variations must be simulated in parallel, from equipment through process to device and circuit level. Correlations must be traced from their source to the final result. In this paper the approach implemented in the cooperative European project SUPERAID7 to reach these goals is presented.