Trade-Off between Gate Oxide Integrity and Transistor Performance for FinFET Technology. (3rd August 2017) - Lo, Hsien-Ching; Peng, Jianwei; Yong, Chloe; Uppal, Suresh; Qi, Yi; Zhan, Hui; Shen, Yan Ping; Chen, Xiaobo; Yan, Jianghu; Zhu, Baofu; Shintri, Shashidhar; Yamaguchi, Shimpei; et al.
Abstract : This work reports that, for the first time, the engineering of eSiGe proximity and eSiGe layer-one (L1) thickness modulates gate oxide integrity and device performance simultaneously in the leading edge FinFET technology. It is observed that there is a tradeoff between the benefit of transistor performance and the cost of gate oxide breakdown voltage (Vbd) degradation. TEM analysis indicates that eSiGe L1 is exposed to interfacial-layer/high-K in replaced-metal-gate (RMG) processes, suggesting gate oxide Vbd is compromised by germanium oxide formation at the L1 and high-k boundary. Thus, the strategy of FinFET junction optimization needs to consider not only transistor performance but also the gate oxide integrity.