A Combined Gas Cluster Ion Beam (GCIB) and Chemical-Mechanical Polish (CMP) Planarization Scheme for Tungsten Replacement Metal Gate (W-RMG). (1st June 2016)

• Record Type: Journal Article
• Authors: Tseng, Wei-Tsu; Long, Justin; Mohan, Kaushik; Kagalwala, Taher; Wu, Changhong; Truong, Connie
• Is Part Of: ECS journal of solid state science and technology. Volume 5:Number 7(2016)
• Page Start: P404
• Page End: P408
• Publication Date: 2016-06-01
• Subjects: GCIB -- RIE -- RMG -- W CMP; Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2.0161607jss
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : Conventional approaches to CMP planarity and uniformity often include the optimization of carrier zone pressure, platen/carrier rotation, slurry flow, conditioning sweep profile etc. Advances in CMP equipment technologies have also enabled new possibility such as multi-zone carrier pressure control through APC for within-wafer non-uniformity (WiWNU) reduction. Other widely-adopted approaches include the use of high-selectivity of slurries to "stop dead" on the final layer of interests without creating excessive local topography due to oxide erosion. While all the above approaches prove effective to certain degree, they are, by nature, wafer-level to sub wafer-level processes. As a consequence, it is difficult for them to differentiate between adjacent chips locally, for example, and correct the non-uniformity to the range of a few nanometers across the wafer as required by RMG module for 22 nm technology nodes and beyond. In this contribution, a novel planarization scheme for RMG is presented to enable nano-scale gate height uniformity control across all dies on 300 mm wafers. The new scheme begins with conventional high-selectivity CMP process (pass-1 W-CMP) to remove overburden and polish the gate height down to a few nanometers thicker than the final target, followed by all-chip gate height measurement on all wafers. Then the gate height data are fed forward to a GCIB tool, where location-specific process (LSP) takes place to trim the oxide down to a pre-determined target, chip by chip . This is followed by a final tungsten touch-up CMP process with high tungsten-to-oxide selectivity to level off the protruded metal patterns and drive the gate height to final target.