OpenBNG: Central office network functions on programmable data plane hardware. Issue 1 (12th August 2020)

• Record Type: Journal Article
• Authors: Kundel, Ralf; Nobach, Leonhard; Blendin, Jeremias; Maas, Wilfried; Zimber, Andreas; Kolbe, Hans‐Joerg; Schyguda, Georg; Gurevich, Vladimir; Hark, Rhaban; Koldehofe, Boris; Steinmetz, Ralf
• Other Names: Zincir‐Heywood Nur guestEditor.; Badonnel Rémi guestEditor.
• Is Part Of: International journal of network management. Volume 31:Issue 1(2021)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2020-08-12
• Subjects: Computer networks -- Management -- Periodicals; 004.6
• DOI: 10.1002/nem.2134
• Languages: English
• ISSNs: 1055-7148

Abstract

Summary: Telecommunication providers continuously evolve their network infrastructure by increasing performance, lowering time to market, providing new services, and reducing the cost of the infrastructure and its operation. Network function virtualization (NFV) on commodity hardware offers an attractive, low‐cost platform to establish innovations much faster than with purpose‐built hardware products. Unfortunately, implementing NFV on commodity processors does not match the performance requirements of the high‐throughput data plane components in large carrier access networks. Therefore, programmable hardware architectures like field programmable gate arrays (FPGAs), network processors, and switch silicon supporting the flexibility of the P4 language offer a promising way to account for both performance requirements and the demand to quickly introduce innovations into networks. In this article, we propose a way to offer residential network access with programmable packet processing architectures. On the basis of the highly flexible P4 programming language, we present a design and open source implementation of a broadband network gateway (BNG) data plane that meets the challenging demands of BNGs in carrier‐grade environments. In addition, we introduce a concept of hybrid openBNG design, realizing the required hierarchical quality of service (HQoS) functionality in a subsequent FPGA. The proposed evaluation results show the desired performance characteristics, and our proposed design together with upcoming P4 hardware can offer a giant leap towards highest performance NFV network access.