Advanced implementation of Montgomery Modular Multiplier. (December 2020) - Abd-Elkader, Ahmed A.H.; Rashdan, Mostafa; Hasaneen, El-Sayed A.M.; Hamed, Hesham F.A.
Abstract: This paper presents an advanced hardware implementation of Modular Multiplication based on Montgomery Modular Multiplier (MMM) architecture. The proposed algorithm is a modification of radix-2 MMM algorithm. The proposed design is implemented on Xilinx Virtex-6 FPGA. The precomputation addition of the modulus and multiplicand, besides removing the final subtraction process, have enhanced the maximum frequency of the design on FPGA. The new modifications have improved the performance and reduced the area of the MMM hardware module. The proposed architecture occupies 908 LUT and 1318 LUT for 256-bit and 512-bit modular multiplier, respectively, for any modulus. Comparing with other related designs our design occupies the smallest area, and has a better efficiency. The proposed design has enhanced the efficiency in the range between 1.41 and 8.7 times the efficiency of other compared designs. The proposed design is intended for lightweight hardware applications of cryptographic modules that is utilized in the Internet of Things (IoT) and the System on Chip (SoC) devices.