Novel junctionless silicon–oxide–nitride–oxide–silicon memory devices with field-enhanced poly-Si nanowire structure. (6th July 2015)

• Record Type: Journal Article
• Authors: Chou, Chia-Hsin; Chan, Wei-Sheng; Wu, Chun-Yu; Lee, I-Che; Liao, Ta-Chuan; Wang, Chao-Lung; Wang, Kuang-Yu; Cheng, Huang-Chung
• Is Part Of: Japanese journal of applied physics. Volume 54:Number 8(2015:Aug.)
• Publication Date: 2015-07-06
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.54.084201
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: In this work, a novel gate-all-around (GAA) low-temperature poly-Si (LTPS) junctionless (JL) silicon–oxide–nitride–oxide–silicon (SONOS) nonvolatile memory device with a field-enhanced nanowire (NW) structure has been proposed to improve the programing/erasing (P/E) performance. Each nanowire has three sharp corners fabricated by a sidewall spacer formation technique to obtain high local electrical fields. Owing to the higher carrier concentration in the channel and the high local electrical field from the three sharp corners, such a JL SONOS memory device exhibits a significantly enhanced P/E speed, a larger memory window, and better data retention properties than a conventional inversion mode NW-channel memory device.