Physisorbed-precursor-assisted atomic layer deposition of reliable ultrathin dielectric films on inert graphene surfaces for low-power electronics. (16th September 2016)

• Record Type: Journal Article
• Authors: Jeong, Seong-Jun; Kim, Hyo Won; Heo, Jinseong; Lee, Min-Hyun; Song, Hyun Jae; Ku, JiYeon; Lee, Yunseong; Cho, Yeonchoo; Jeon, Woojin; Suh, Hwansoo; Hwang, Sungwoo; Park, Seongjun
• Is Part Of: 2D materials. Volume 3:Number 3(2016)
• Publication Date: 2016-09-16
• Subjects: graphene -- atomic layer deposition -- scanning tunnelling microscopy -- capacitance equivalent oxide thickness -- subthreshold swing; Graphene -- Periodicals; Materials science -- Periodicals; Nanostructured materials -- Periodicals; 620.115
• DOI: 10.1088/2053-1583/3/3/035027
• Languages: English
• ISSNs: 2053-1583

Abstract

Abstract: Among the most fundamental challenges encountered in the successful incorporation of graphene in silicon-based electronics is the conformal growth of ultrathin dielectric films, especially those with thicknesses lower than 5 nm, on chemically inert graphene surfaces. Here, we present physisorbed-precursor-assisted atomic layer deposition (pALD) as an extremely robust method for fabricating such films. Using atomic-scale characterisation, it is confirmed that conformal and intact ultrathin Al2 O3 films can be synthesised on graphene by pALD. The mechanism underlying the pALD process is identified through first-principles calculations based on density functional theory. Further, this novel deposition technique is used to fabricate two types of wafer-scale devices. It is found that the incorporation of a 5 nm-thick pALD Al2 O3 gate dielectric film improves the performance of metal-oxide-graphene field-effect transistors to a greater extent than does the incorporation of a conventional ALD Al2 O3 film. We also employ a 5 nm-thick pALD HfO2 film as a highly scalable dielectric layer with a capacitance equivalent oxide thickness of 1 nm in graphene-based tunnelling field-effect transistors fabricated on a glass wafer and achieve a subthreshold swing of 30 mV/dec. This significant improvement in switching allows for the low-voltage operation of an inverter within 0.5 V of both the drain and the gate voltages, thus paving the way for low-power electronics.