Analyzing the interface trap density in SiGe capacitors using an abnormal flat band voltage shift at low temperature. (5th November 2020) - Sun, Li-Chuan; Lin, Chih-Yang; Chen, Po-Hsun; Tsai, Tsung-Ming; Zhou, Kuan-Ju; Tu, Yu-Fa; Huang, Wei-Chen; Tseng, Yi-Ting; Tan, Yung-Fang; Lin, Shih-Kai; Lin, Chun-Chu; Hung, Wei-Chun; et al.
Abstract: In this work, capacitance-voltage ( C – V ) measurement and analysis were performed on silicon (Si)-based devices at low temperature (77 K). By this method, the C – V curves were compared for two devices with channel materials of Si and silicon–germanium (SiGe). The lattice mismatch of SiGe results in more defects at the interface between the channel and the gate insulator layer, which cause abnormal C – V properties. Through comprehensive theoretical calculation, proved by Silvaco simulation, an energy band diagram and physical model are proposed. Furthermore, the distribution of donor-like states can be examined, which can assist in monitoring the interface quality.