Junctionless versus inversion-mode lateral semiconductor nanowire transistors. (3rd September 2018)

• Record Type: Journal Article
• Authors: Veloso, A; Matagne, P; Simoen, E; Kaczer, B; Eneman, G; Mertens, H; Yakimets, D; Parvais, B; Mocuta, D
• Is Part Of: Journal of physics. Volume 30:Number 38(2018)
• Publication Date: 2018-09-03
• Subjects: nanowire FETs -- CMOS scaling -- junctionless and inversion-mode type of transistors -- DC and analog/RF performance -- reliability -- variability -- noise; Condensed matter -- Periodicals; Matière condensée -- Périodiques; Vaste stoffen; Vloeistoffen; Natuurkunde; Electronic journals; Computer network resources; 530.4105
• DOI: 10.1088/1361-648X/aad7c7
• Languages: English
• ISSNs: 0953-8984

Abstract

Abstract: This paper reports on gate-all-around silicon nanowire field-effect transistors (FETs) built in a lateral configuration, which represent the ultimate scaling limit of triple-gate finFET devices and allow a less disruptive CMOS scaling path in terms of processing and circuit layout design. We address several of their critical technological challenges, looking in particular at doping strategies. A comprehensive review of junctionless versus inversion-mode type of transistors is here presented, evaluating the impact on the devices' operation mode and on device properties such as: variability, reliability, noise, DC and analog/RF performance. We also discuss the potential for further manufacturable co-integration options.