Organic light‐emitting diode display pixel circuit employing double‐gate low‐temperature poly‐Si thin‐film transistor and metal‐oxide thin‐film transistors. Issue 12 (1st September 2020)

• Record Type: Journal Article
• Authors: Lee, JoonHo; Kim, DaeHyun; Yang, JooWon; Moon, KookChul; Lee, Soo‐Yeon; Jeon, JaeHong; Kim, YongSang; Choi, SeungChan; Chung, UiJin; Park, KwonShik; Park, KeeChan
• Is Part Of: Journal of the Society for Information Display. Volume 28:Issue 12(2020)
• Page Start: 1003
• Page End: 1011
• Publication Date: 2020-09-01
• Subjects: double‐gate -- low‐temperature polycrystalline silicon and oxide (LTPO) -- organic light‐emitting diode (OLED) -- pixel circuit -- thin‐film transistor (TFT); Information display systems -- Periodicals; 621.38154205
• DOI: 10.1002/jsid.961
• Languages: English
• ISSNs: 1071-0922

Abstract

Abstract: An organic light‐emitting diode (OLED) display pixel circuit composed of a double‐gate (DG) low‐temperature polycrystalline silicon (LTPS) thin‐film transistor (TFT) and metal‐oxide (MO) TFTs is reported. Two control lines used to initialize the gate‐to‐source bias (VGS ) of the driving TFT in the conventional pixel circuit are eliminated by modulating the bottom gate bias (VBS ) of the DG‐LTPS TFT. Low leakage current of MO TFT enables us to adopt the simultaneous‐emission scheme for arbitrary compensation time setting and 1‐Hz frame rate driving for low power consumption without flicker. The proposed circuit exhibits better compensation results and smaller area compared with the conventional low‐temperature polycrystalline silicon and oxide (LTPO) pixel circuit. The pixel density of 538 pixels per inch (ppi) has been obtained employing 2‐μm design rule. Abstract : An OLED display pixel circuit composed of a double‐gate (DG) LTPS TFT and metal‐oxide (MO) TFTs is reported. Two control lines used to initialize the gate‐to‐source bias (VGS ) of the driving TFT in the conventional pixel circuit are eliminated by modulating the bottom gate bias (VBS ) of the DG‐LTPS TFT. (A) Circuit diagram of proposed LTPO 4T‐2C‐5L pixel circuit with DG driving TFT and (B) operation timing diagram.