Circuit design using Schmitt Trigger to reliability improvement. (November 2020) - Zimpeck, A.L.; Meinhardt, C.; Artola, L.; Hubert, G.; Kastensmidt, F.L.; Reis, R.A.L.
Abstract: This paper presents a design strategy to reduce the impact of process variations and soft error susceptibility in FinFET circuits. The mitigation is provided by connecting a Schmitt Trigger at the logic gate output. The improvements in power and delay variability can reach up to 32.6% and 42.1%, respectively, with logic cells almost immune to soft error even at the near-threshold regime. When compared with other circuit-level methods such as sleep transistor, decoupling cells, and transistor reordering, on average, the Schmitt Trigger technique is at least 6%, 8%, and 10.5% more robust to process variability, respectively. Highlights: Explore circuit-level approaches in FinFET designs to mitigate process variability and soft errors. The improvement in power and delay variability can reach to 32.6% and 42.1%, respectively, using the Schmitt Trigger design. A circuit design using Schmitt Trigger is immune to soft errors even at the near-threshold regime. Larger Schmitt Triggers decrease the impact on power variability considerably. The Schmitt Trigger is more advisable for designs with huge reliability concerns due to overhead in area, delay, and power.