Design exploration of majority voter architectures based on the signal probability for TMR strategy optimization in space applications. (November 2020) - Aguiar, Y.Q.; Wrobel, F.; Autran, J.-L.; Leroux, P.; Saigné, F.; Pouget, V.; Touboul, A.D.
Abstract: Hardware redundancy is a well-known fault tolerance technique used in safety- and mission-critical systems. However, the hardening efficiency of such techniques relies on the robustness of the majority voter circuitry. This summary provides the design exploration of majority voter architectures to be used in radiation environments such as in space missions. An application-specific Single-Event Transient (SET) characterization based on the signal probability is proposed to optimize the Triple-Modular Redundancy (TMR) block insertion methodologies. Results show that the SET cross-section of complex-gate architectures presents low input dependence while for the NOR/NAND based architectures a higher dependence is observed due to the logical masking effects. Additionally, different from the other architectures, the NAND voter has shown a reduction in the SET rate as the signal probability is increased. Considering the signal probability p  = 0.1, p  = 0.5 and p  = 0.9, the best design for the two analyzed orbits is the NOR, CMOS1 and NAND voter, respectively.