AC stress reliability study on a novel vertical MOS transistor for non-volatile memory technology. (November 2020) - Locati, J.; Della Marca, V.; Rivero, C.; Fornara, P.; Regnier, A.; Niel, S.; Coulié, K.
Abstract: This paper presents a novel high voltage vertical trench MOS transistor designed to be used in a Non-Volatile Memory (NVM) technology. Huge hump effect is demonstrated explaining some phenomenon observed during the AC stress. Quasi-static measurements are also reported showing that this vertical trench MOS transistor can be suitable for the use in an NVM environment. Finally, the AC stress reliability results demonstrate significant instabilities of both parasitic and main transistors. The comprehension is supported by TCAD simulations. Highlights: Novel vertical trench MOS transistor for non-volatile memory technology Leakage current understanding assisted by TCAD simulation Reliability performances linked to parasitic transistors degradation Performances and scalability improvement