Integrable Quasivertical GaN U‐Shaped Trench‐Gate Metal‐Oxide‐Semiconductor Field‐Effect Transistors for Power and Optoelectronic Integrated Circuits. Issue 7 (7th November 2019) - Guo, Zhibo; Hitchcock, Collin; Karlicek, Robert F.; Piao, Guanxi; Yano, Yoshiki; Koseki, Shuuichi; Tabuchi, Toshiya; Matsumoto, Koh; Bulsara, Mayank; Chow, T. Paul
Abstract : Integrable, hexagonal‐cell, high‐voltage, quasivertical GaN power U‐shaped trench‐gate metal‐oxide‐semiconductor field‐effect transistors (UMOSFETs) fabricated in the n+/p/n−/n+ GaN epilayers on sapphire substrates are experimentally demonstrated for the first time. Hexagonal cells, with pitch ranging from 11 to 20 μm, are used to obtain identical m ‐plane sidewalls for gate and drain trenches. Metallization compatible with light‐emitting diode (LED) optoelectronic integration is used. The dependence of device performance on different parameters is systematically studied and analyzed. The lowest R on, sp of 23 mΩ cm 2 and highest drain saturation current of 295 A cm −2 are obtained by measuring an 11 μm cell‐pitch UMOSFET. The breakdown voltage of an open‐cell design variation (208 V) is higher than that of a closed‐cell design variation (89 V), whereas the closed‐cell design exhibits a lower off‐state leakage current of 1.4 × 10 −5 A cm −2 . A hexagonal‐cell specific on‐state resistance R cell, sp of 8.5 mΩ cm 2 and buried n+ layer sheet resistance R BL, □ of 223 Ω □ −1 are extracted by applying a 2D resistance network model to UMOSFETs of varying sizes. Abstract : Integrable, hexagonal‐cell, high‐voltage, quasivertical GaN power U‐shaped trench‐gate metal‐oxide‐semiconductor field‐effect transistors (UMOSFETs) are experimentally demonstrated for the first time. Hexagonal cells are used to obtain identical m ‐plane sidewalls for gate and drain trenches. Metallization compatible with light‐emitting diode (LED) optoelectronic integration is used. The dependence of device performance on different parameters is systematically studied and analyzed.