Soft error hardening enhancement analysis of NBTI tolerant Schmitt trigger circuit. (April 2020) - Shah, Ambika Prasad; Rossi, Daniele; Sharma, Vishal; Vishvakarma, Santosh Kumar; Waltl, Michael
Abstract: Bias temperature instability (BTI) and soft errors are major reliability concerns for deep submicron technologies. Negative BTI leads to an increase of the threshold voltage of PMOS transistors and is thus considered a serious challenge for improving circuit performance. In this paper, we concentrate on a design-time solution, i.e., more reliable NMOS only Schmitt Trigger with Voltage Booster (NST-VB). For this we analyzed the impact of BTI on the soft-error susceptibility of different CMOS circuits using HSPICE and performed critical charge simulations considering different supply voltages and stress time. From our results, we conclude that the NST-VB circuit has a higher critical charge when compared to CMOS inverters and Schmitt trigger (ST) based counterparts. NST-VB has improved the sensitivity of 62.48% and 55.10%, as compared to CMOS inverter and ST circuits, respectively, after three years of operation. To better assess soft error resilience, we introduce a soft error rate ratio (SERR) as a performance metric. Our analysis indicates that NST-VB has 12.62%, and 12.39% less SERR compared to ST and CMOS inverters. The effect of process variation on CMOS inverter, ST inverter and NST-VB circuit are analyzed using 5000 Monte Carlo simulations for critical voltages and we observe that the deviation of NST-VB is 6.06× and 6.89× less as compared to the CMOS and ST based inverters, respectively. Highlights: Soft error tolerance analysis of BTI resilient Schmitt trigger circuit has been performed. Soft error rate with and without BTI stress has been calculated. Critical charge sensitivity with the stress time for CMOS, Schmitt trigger and NST-VB based inverter circuits has been analysed. For the process variability analysis on the circuits, 5000 Monte Carlo simulations for the critical voltages has been performed.