CAD-II: the second version current-mode readout ASIC for high-resolution timing measurements. (18th July 2016)

• Record Type: Journal Article
• Authors: Yuan, Z.X.; Deng, Z.; Wang, Y.; Liu, Y.N.
• Is Part Of: Journal of instrumentation. Volume 11:Number 7(2016:Jul.)
• Page Start: P07013
• Page End: P07013
• Publication Date: 2016-07-18
• Subjects: Analogue electronic circuits -- CMOS readout of gaseous detectors -- Front-end electronics for detector readout -- Resistive-plate chambers; Scientific apparatus and instruments -- Periodicals; 502.84
• DOI: 10.1088/1748-0221/11/07/P07013
• Languages: English
• ISSNs: 1748-0221

Abstract

Abstract: This paper presents the second version of a fully current-mode front-end ASIC, CAD (Current Amplifier and Discriminator), for MRPC detectors for TOF applications. Several upgrades have been made in this new version, including: 1). Using differential input stages with input impedance down to 30 Ω and LVDS compatible outputs; 2). Much higher current gain and bandwidth of 4.5 A/A and 380 MHz ; 3). Fabricated in 0.18 μ m CMOS process instead of 0.35 μ m CMOS technology used in CAD-I. The detailed design of the ASIC will be described as well as the measurement results. The single-ended input impedance could be as low as 32 Ω and the power consumption was measured to be 15 mW per channel. Input referred RMS noise current was about 0.56 μ A . The threshold could be set as low as 4.5 μ A referred to input, corresponding to 9 fC for the typical MRPC detector signal with 2 ns width. Sub- 10 ps resolution has been measured for input signal above 200 μ A .