New simple transistor realizations of second‐ generation voltage conveyor. (27th September 2020) - Yesil, Abdullah; Minaei, Shahram
Summary: In this paper, two new complementary metal oxide semiconductor (CMOS) realizations for second‐generation voltage conveyor (VCII) are presented. The first proposed VCII has a very simple structure employing only six transistors. The second proposed VCII employs 11 transistors, and none of the transistors at both proposed circuits suffer from the body effect. Small‐signal analysis, parasitic elements, and input‐referred noise of the proposed VCIIs are given. Moreover, a new active element called voltage controlled second‐generation voltage conveyor (VC‐VCII) is proposed as dual element of current controlled second‐generation current conveyor (CCCII) active element. Its parasitic resistance at the Y terminal can be controlled electronically. Two presented CMOS structures of VCII are worked as VC‐VCII with slight modification. Proposed circuits are simulated in Cadence Analog environment using TSMC 0.18‐μm process parameters with ±0.9‐V supply voltages. Both CMOS structures occupy a small chip area of 276.8 and 271 μm 2, respectively. The bandwidth of the current follower stage of the proposed VCIIs is found as 794 MHz, whereas the bandwidth of the voltage follower stage for the first and second proposed VCIIs is found as 2.57 and 1.92 GHz, respectively. As an application example, voltage‐mode first‐order low‐pass filter has been given with its tunable gain by using VC‐VCII. Abstract : This paper presented two new CMOS realizations for second‐generation voltage conveyor (VCII). The first proposed VCII has a simple structure employing only six transistors. The second proposed VCII employs 11 transistors, and none of the transistors at both proposed circuits suffer from the body effect. Moreover, new active element called voltage‐controlled VCII (VC‐VCII) is proposed as dual element of current controlled second‐generation current conveyor (CCCII) active element. Proposed circuits are simulated in Cadence Analog environment using TSMC 0.18‐μm process parameters.