An enhancement-mode pseudomorphic high electron mobility transistor prepared by an Electroless Plating (EP) and a gate-sinking approaches. (March 2015) - Chen, Chun-Chia; Chen, Huey-Ing; Liu, I-Ping; Chou, Po-Cheng; Liou, Jian-Kai; Tsai, Jung-Hui; Liu, Wen-Chau
Highlights: An enhancement-mode PHEMT (EPHEMT) was achieved by Electroless Plating (EP) deposition and gate-sinking approaches. The use of low-temperature EP provides good gate-Schottky properties. A direct-couple FET logic (DCFL), i.e., an inverter circuit, was completed by using an EP-based EPHEMT as a driver. Temperature-dependent current–voltage ( I – V ) characteristics of an EP-based EPHEMT were comprehensively studied. Abstract: An enhancement-mode PHEMT (EPHEMT), fabricated by Electroless Plating (EP) and gate-sinking approaches, is comprehensively studied under high-temperature ambiences (300–475 K). The interdiffusion at Pd/AlGaAs interface confirmed by Auger depth spectroscopy (AES) profile analysis leads to the modulation of threshold voltage. In addition, the corresponding Pd-gate morphologies are examined through atomic force microscopy (AFM) and scanning electron microscopy (SEM). By gate-sinking (525 K), an EP-based PHEMT with threshold voltage shifting of +0.33 V is converted to an E-mode operation. Based on inherent advantages of EP-gate formation, the studied EPHEMT shows excellent DC performance and well thermal stability. With a gate dimension of 1 × 100 μm 2, the studied EPHEMT presents low gate current of 6.5 (74.5) μA/mm, maximum extrinsic transconductance of 185.2 (150.6) mS/mm, maximum drain saturation current of 219.9 (98.8) mA/mm, and threshold voltage of 0.203 (0.196) V at 300 (475) K. In addition, the thermal stabilities on gate current, extrinsic transconductance, and drain current are found for the studied EPHEMT. Furthermore, a designed direct-coupled FET logic (DCFL) inverter, combined with an EP-gate and a thermal evaporated (TE)-gate PHEMT, is achieved and characterized.