Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG. (October 2016) - Kushwaha, Pragya; Bala Krishna, K.; Agarwal, Harshit; Khandelwal, Sourabh; Duarte, Juan-Pablo; Hu, Chenming; Chauhan, Yogesh Singh
Abstract: The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance ( R th ). Further, R th increases with reduction in channel length ( L g ). In this paper, we have proposed a compact model for the geometry and temperature dependence of R th in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors. Abstract : Graphical abstract: The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance ( Rth ). Further, Rth increases with reduction in channel length ( Lg ). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. We also validate the radio-frequency (RF) model with measured high frequency data. The proposed model is implemented in the independent multigate model (BSIM-IMG) for FDSOI transistors. Abstract : Highlights: Geometrical scaling of thermal resistance in FDSOI transistor has been analyzed. A new behavioral model for thermal resistance scaling has been proposed. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The BSIM-IMG model is validated on the measured RF characteristics for wide bias and frequency ranges.