Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators. (September 2020)

• Record Type: Journal Article
• Authors: Jasemi, Masoomeh; Hessabi, Shaahin; Bagherzadeh, Nader
• Is Part Of: Computers & electrical engineering. Volume 86(2020)
• Publication Date: 2020-09
• Subjects: CNN -- MLC STT-RAM -- Floating-point -- Accelerators -- Deep Neural Network -- Low Power Buffer; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2020.106698
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: We propose a lightweight scheme where the formation of a data block is changed in such a way that it can tolerate soft errors significantly better than the baseline. The key insight behind our work is that CNN weights are normalized between -1 and 1 after each convolutional layer, and this leaves one bit unused in half-precision floating-point representation. By taking advantage of the unused bit, we create a backup for the most significant bit to protect it against the soft errors. Also, considering the fact that in MLC STT-RAMs the cost of memory operations (read and write), and reliability of a cell are content-dependent (some patterns take larger current and longer time, while they are more susceptible to soft error), we rearrange the data block to minimize the number of costly bit patterns. Combining these two techniques provides the same level of accuracy compared to an error-free baseline while improving the read and write energy by 9% and 6%, respectively.