Recycling of unused leakage current for energy efficient multi-voltage systems. (July 2020)

• Record Type: Journal Article
• Authors: Hossain, MD Shazzad; Savidis, Ioannis
• Is Part Of: Microelectronics journal. Volume 101(2020)
• Publication Date: 2020-07
• Subjects: Leakage reuse system-on-chips (SoCs) multi-voltage systems energy-efficient computing voltage stacking sub-threshold computing; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104782
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A novel method for the delivery of power to sub-threshold (sub- V t ) circuits is proposed. The unused leakage current during the idle-mode operation of super-threshold (super- V t ) circuits is used to supply current to the sub- V t circuits. Super- V t and sub- V t circuits are characterized in a 45 nm CMOS technology, where the super- V t circuits operate at 1.2 V and generate a sub- V t voltage of 380 mV. The energy break-even point of the leakage reuse technique is analyzed both analytically and through simulation. The proposed technique is compared with two conventional methods, one that implements separate power distribution networks for the super- V t and sub- V t circuits (baseline) and the second that applies voltage stacking. The proposed leakage reuse technique implemented on the s27 ISCAS89 benchmark circuit reduces the average and peak power consumption to, respectively, 0.41× and 0.7× that of the baseline technique, while also reducing the peak voltage noise on the true ground node VSS and the settling time of the true ground voltage V SS to, respectively, 0.68× and 0.44× at a cost of a 1.24× increase in the FO4 delay. The leakage reuse technique implemented on the s208 ISCAS89 benchmark circuit resulted in a reduction of the peak voltage noise on the virtual ground node VGND and a reduction in the settling time of the virtual ground voltage V GND to, respectively, 0.28× and 0.23× that of the voltage stacking technique. In addition, the regulation of the sub- V t supply voltage is evaluated for a variable workload executing on a 32-bit RISC-V core operating at 380 mV.