A Self‐Terminated Operation Scheme for High‐Parallel and Energy‐Efficient Forming of RRAM Array. (25th February 2020)

• Record Type: Journal Article
• Authors: Feng, Yulin; Huang, Peng; Zhang, Yizhou; Shen, Wensheng; Xu, Weijie; Xiang, Yachen; Ding, Xiangxiang; Zhao, Yudi; Gao, Bin; Wu, Huaqiang; Qian, He; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng
• Is Part Of: Advanced Electronic Materials. Volume 6:Number 4(2020)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2020-02-25
• Subjects: forming -- resistive random access memory -- self‐terminated operation -- wire capacitance; Materials -- Electric properties -- Periodicals; Materials science -- Periodicals; Magnetic materials -- Periodicals; Electronic apparatus and appliances -- Periodicals; 537
• DOI: 10.1002/aelm.201901324
• Languages: English
• ISSNs: 2199-160X

Abstract

Abstract: By introducing a capacitor in series (CST ), a self‐terminated (ST) operation scheme is proposed to achieve high‐parallel forming of resistive random access memory (RRAM) array with reduced time and energy consumption. Once the RRAM cell is switched to the low‐resistance state, the current is automatically cut off by the capacitor, which can significantly improve the parallelism and energy efficiency. The wire capacitance of interconnect ( C wire ) can be utilized as CST, which means there is no addition circuit or process expense for the proposed ST scheme. After successful experimental verification of the proposed ST operation scheme in 1 kb RRAM array, the performance of 1 Gb RRAM memory is evaluated, which shows × 10 3 improvement in forming time (from 0.6 h to 0.84 s) and × 10 4 improvement in energy consumption. Moreover, by experimentally leveraging the operation scheme for array forming, the operation current is reduced in subsequent switching process without deteriorating the device reliability, which demonstrates the feasibility of the proposed ST operation scheme and its potential in low power applications. Abstract : A self‐terminated operation scheme is proposed with a series capacitor, which can be implemented by wire capacitances, to achieve high‐parallel forming of RRAM array with reduced time and energy consumption. The proposed operation scheme is verified in experiment and simulation and shows no deterioration of switching characteristics, indicating the feasibility of the proposed scheme.