A 2–20 GHz SiGe HBT single-stage cascode LNA with linearity enhancement. (April 2019)

• Record Type: Journal Article
• Authors: Li, Zhenrong; Liu, Shuang; Zhang, Chaoyue; Zhuang, Yiqi
• Is Part Of: Microelectronics journal. Volume 86(2019)
• Page Start: 130
• Page End: 139
• Publication Date: 2019-04
• Subjects: Low noise amplifier -- Linearity -- Cascode -- Passive network -- SiGe HBT; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2019.03.001
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A wideband high-gain low-noise amplifier (LNA) with improved linearity is presented in this paper. To suppress the gain compression of large signal under high gain conditions, the single-stage cascode topology using resistive shunt-shunt feedback and an emmiter degenerate resistor are adopted. Wideband input matching is thus realized in conjunction with the preceding L-type passive network. A passive network inserted between the cascode structure and load enhances the gain bandwidth as well as the impedance matching. The LNA is based on a 0.18μm SiGe HBT BiCMOS process and the post simulation results show that the LNA features 2–20 GHz bandwidth, 16.1–18.1 dB power gain and 2.5–3.7 dB noise figure (NF). It exhibits input 1-dB compression point of −12dBm above 14 GHz and consumes 55 mW power form a 3.3-V supply. The chip size is 0.435 mm 2 without pads.