An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger. (October 2020)

• Record Type: Journal Article
• Authors: Vidhyadharan, Sanjay; Dan, Surya Shankar; Yadav, Ramakant; Hariprasad, Simhadri
• Is Part Of: Microelectronics journal. Volume 104(2020)
• Publication Date: 2020-10
• Subjects: Schmitt trigger -- 45 nm CMOS technology -- Ion: Ioff ratio -- Power delay product -- Nanoscale GOTFET -- Verilog-A; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104879
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield around double the on current I on, while the off current I off remains around an order lower, than that of an analogous equally-sized MOSFET at the same technology node. Higher I on : I off ratio and steeper sub-threshold slope of the proposed GOTFETs make them ideal candidates for ultra-low voltage applications like Schmitt trigger circuits. Considering the superior performance of the proposed GOTFET devices, simply replacing the MOSFETs with the proposed GOTFETs in conventional Schmitt trigger circuit significantly reduces the delays and static power consumption of the circuit as expected. At 0.4 V power supply voltage, there is 91.7% improvement in Power Delay Product (PDP) for Complementary GOTFET (CGOT) based conventional Schmitt trigger as compared to CMOS conventional Schmitt trigger for the same hysteresis width of 120 mV. In order to further minimize the dynamic power, a novel CGOT regenerative-latch Schmitt trigger design has also been presented in this paper for the first time, which further reduces the total (static + dynamic) power consumption and delays of the conventional Schmitt trigger circuit. The overall PDP in the proposed CGOT regenerative-latch based Schmitt trigger has been demonstrated to be merely 1.9% of (98.1% lower than) the PDP in corresponding CMOS conventional design.