CNFET based design of unbalanced ternary circuits using efficient shifting literals. (October 2020)

• Record Type: Journal Article
• Authors: Sharma, Trapti; Kumre, Laxmi
• Is Part Of: Microelectronics journal. Volume 104(2020)
• Publication Date: 2020-10
• Subjects: Carbon nano tube field effect transistor -- Multiple valued logic -- Multi ternary digit multiplier -- Ternary arithmetic circuits; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104869
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Multi-valued logic design provides the benefit of increased integration by reducing the interconnections which is the main source of power dissipation in the VLSI chip. As compared to conventional binary logic representation, ternary logic representation helps to represent more amount of information over the same number of digits. Hence this work presents the design of ternary adder, subtractor, multiplier and parallel adder/subtractor with enhanced performance in carbon nanotube field effect transistor (CNFET) technology. The addition and subtraction operations are set into a single unit, exploiting the advantage of ternary logic to increase the processing capability of the module. The presence of symmetricity among single shift and dual shift operators while realizing addition/subtraction operation further favors the combing of adder/subtractor blocks. Then 4-stage parallel adder/subtractor is designed. Further single-trit and multi-trit multiplier circuits are also implemented by employing the proposed adder and multiplier units. All the proposed arithmetic designs are derived from the proposed ternary multiplexer and shifting operator circuits. To test the efficiency of proposed circuits, the simulations are conducted on 32 nm CNFET technology using Synopsis HSPICE simulator. In the proposed methodology reduction in power consumption of 38% for combined adder/subtraction block and 40% for parallel adder/subtractor unit is obtained. Furthermore, for the multi trit adder/subtractor and multiplier designs, the maximum power delay product (PDP) improvement up to 66% is achieved.