An analysis of computational models for accelerating the subtractive pixel adjacency model computation. (April 2015)

• Record Type: Journal Article
• Authors: Rodriguez-Perez, Marisol; Morales-Reyes, Alicia; Cumplido, René; Feregrino-Uribe, Claudia
• Is Part Of: Computers & electrical engineering. Volume 43(2015)
• Page Start: 9
• Page End: 16
• Publication Date: 2015-04
• Subjects: Steganalysis -- SPAM -- FPGA -- CUDA -- GPU; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2015.01.004
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: Two computational parallel models are developed using FPGA and GPU platforms. To the best of our knowledge, these are the first acceleration schemas for SPAM. An architectural and performance analysis of both computational models is presented. The FPGA architecture accelerates SPAM making an optimal use of hardware resources. The GPU model accelerates SPAM's 1st stage facing a bottleneck on its 2nd stage. Abstract: Detecting covert information in images by means of steganalysis techniques has become increasingly necessary due to the amount of data being transmitted mainly through the Internet. However, these techniques are computationally expensive and not much attention has been paid to reduce their cost by means of available parallel computational platforms. This article presents two computational models for the Subtractive Pixel Adjacency Model (SPAM) which has shown the best detection rates among several assessed steganalysis techniques. A hardware architecture tailored for reconfigurable fabrics is presented achieving high performance and fulfilling hard real-time constraints. On the other hand, a parallel computational model for the CUDA architecture is also proposed. This model presents high performance during the first stage but it faces a bottleneck during the second stage of the SPAM process. Both computational models are analyzed in detail in terms of their algorithmic structure and performance results. To the best of Authors' knowledge these are the first design proposals to accelerate the SPAM model calculation.