Power-efficient implementation of pseudo-random number generator using quantum dot cellular automata-based D Flip Flop. (July 2020)

• Record Type: Journal Article
• Authors: Senthilnathan, S.; Kumaravel, S.
• Is Part Of: Computers & electrical engineering. Volume 85(2020)
• Publication Date: 2020-07
• Subjects: Complementary Metal Oxide Semi-Conductor (CMOS) -- Quantum dot Cellular Automata (QCA) -- Pseudo-Random Number Generator (PRNG) -- Flip flop -- Polarization -- Power dissipation; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2020.106658
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: Quantum dot cellular automata based D flip flop is proposed to construct Pseudo random number generator. Loop-based technique is used in the D flip flop, in order to minimize the area, latency and power dissipation. Reliability and power dissipation analysis are done to validate the efficacy of the proposed design. Pseudo random number generator is used to build the complex circuits like encryption and decryption blocks for secured communication. Abstract: In secured communication, pseudo-random number generators (PRNGs) are widely used to generate random sequences. This paper presents a novel D flip flop and standard EX-NOR gate to realize a Quantum dot Cellular Automata (QCA) based PRNG. For the purpose of comparison, QCA based PRNG is implemented with existing D flip flops. The proposed D flip flop comprises a cell count of 24 with area of 0.02 µm 2 and delay of 0.05 ps, total power dissipation for D flip flop is 40.30 meV, 49.76 meV and 61.90 meV for different tunneling energy level of 0.5 Ek, 1.0 Ek and 1.5 Ek, respectively at temperature of 2 Kelvin. The implemented PRNG configurations are simulated using QCA Designer tool for area and delay. Power dissipation of D flip flop is analyzed using QCA Pro simulator tool. From the simulated results, it may be noted that PRNG with novel D flip flop realization achieves low power, low area and less delay compared to other PRNG realization. Graphical Abstract: Image, graphical abstract