3D Sidewall Integration of Ultrahigh‐Density Silicon Nanowires for Stacked Channel Electronics. (30th April 2019) - Wu, Xiaoxiang; Ma, Haiguang; Yin, Han; Pan, Danfeng; Wang, Junzhuan; Yu, Linwei; Xu, Jun; Shi, Yi; Chen, Kunji
Abstract: Building 3D electronics represents a promising method for the integration of more functionalities into a given footprint. To this end, stacked multilevel silicon nanowires (SiNWs) are ideal multilevel channels to construct high‐density 3D electronics. 3D vectorial self‐assembled growth of orderly lateral SiNWs is accomplished directly upon oblique or vertical sidewalls, which are otherwise difficult to address by conventional lithography, led by indium droplets that absorb amorphous silicon thin film coated on the sidewalls to produce SiNW stacks at only 350 °C. With the guidance of sidewall terraces formed by multilayer or alternating etching approaches, ultralong supported or suspended multilevel SiNW stacks can be easily mass produced with tailored geometry and average diameter and spacing down to 50 and 100 nm, respectively. Prototype stacked multi‐SiNW‐channel transistors, with a fin‐gate configuration, are also fabricated and demonstrate an impressive high I on / I off current ratio >10 7, a hole mobility of 60 cm 2 /V −1 s −1, and a rather low leakage current. These results highlight the unique potential and versatility of a nanodroplet‐assisted self‐assembled growth in constructing more complex and advanced 3D stacked channel electronics. Abstract : 3D self‐assembled growth of parallel silicon nanowires (SiNWs) is demonstrated, upon oblique/vertical sidewalls, to produce ultralong supported/suspended multilevel SiNW stacks. Prototype stacked channel transistors achieve an impressive high I on / I off current ratio >10 7 and rather low leakage current, indicating a new approach to construct advanced 3D electronics.