Thickness‐Dependent Electronic Transport in Ultrathin, Single Crystalline Silicon Nanomembranes. (12th May 2019)

• Record Type: Journal Article
• Authors: Song, Enming; Guo, Zhongxun; Li, Guodong; Liao, Fuyou; Li, Gongjin; Du, Haina; Schmidt, Oliver G.; Kim, Minju; Yi, Yeonjin; Bao, Wenzhong; Mei, Yongfeng
• Is Part Of: Advanced Electronic Materials. Volume 5:Number 7(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2019-05-12
• Subjects: insulator‐to‐metal transition -- silicon nanomembrane -- surface dipole density -- temperature dependence -- ultrathin thickness; Materials -- Electric properties -- Periodicals; Materials science -- Periodicals; Magnetic materials -- Periodicals; Electronic apparatus and appliances -- Periodicals; 537
• DOI: 10.1002/aelm.201900232
• Languages: English
• ISSNs: 2199-160X

Abstract

Abstract: As distinct from bulk silicon, ultrathin silicon‐on‐insulator (SOI) or silicon nanomembranes (Si‐NMs) offer excellent electronic and mechanical properties that are essential to the development of electronic/optoelectronic systems. Ultrathin Si‐NM field effect transistors (FETs) based on p‐doped SOI (100) wafers are investigated. The thickness of the Si‐NMs is controllably reduced from 50 nm to 10 nm through the use of a unique etching process. Based on systematic investigation of Si‐NM FETs with varying thicknesses, both insulating and metallic behaviors are observed, which can be attributed to carrier enhancement by surface‐dipole doping after thickness reduction. Spectroscopy characterization and theoretical simulations reveal that this high surface‐dipole density can be inverted, yielding high‐density electrons regardless of the bulk p‐doped nature of the material, thus significantly enhancing its conductivity. These findings offer a physical understanding of thickness dependence, which is critical to the future development of ultrathin SOI electronics, of relevance to a diverse range of semiconductor applications. Abstract : Ultrathin Si‐NM field effect transistors (FETs) based on p‐doped SOI (100) wafers are fabricated. The thickness of the FETs is controllably reduced from 50 nm to 10 nm through the use of a unique etching process, and they exhibit high conductivity due to their high surface‐dipole density.