A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications. (6th March 2020)

• Record Type: Journal Article
• Authors: Yang, Wei-Bin; Wang, Hsi-Hua; Chang, Hsin-I; Lo, Yu-Lung
• Is Part Of: Japanese journal of applied physics. Volume 59:Number SG(2020)
• Publication Date: 2020-03-06
• Subjects: PLL -- ADPLL -- Fast-locking -- Phase self-alignment mechanism -- Sub-GHz IoT; Physics -- Periodicals; 621.05
• DOI: 10.35848/1347-4065/ab7276
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: This paper describes a fast-locking all-digital phase-locked loop (ADPLL) with dynamic loop gain control and a phase self-alignment mechanism. Compared with conventional fast-locking ADPLLs, the ADPLL proposed in this paper features the phase self-alignment mechanism to resolve overdamping caused by a large KI . Therefore, the proposed ADPLL not only reduces locking time but also maintains jitter performance. In this paper, we used a 0.18 μ m standard CMOS process with a supply voltage of 1.8 V. The experimental results indicated that the proposed ADPLL can reduce locking time by 91%. The output frequency range of the proposed ADPLL is 0.7–1 GHz, which is suitable for sub-GHz Internet of Things band applications. At 1 GHz, the power consumption was 10.93 mW, peak-to-peak jitter was 19.53 ps, locking time was 3.5 μ s which is 35 TREF, and core area was 0.291 mm 2 .