High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications. (4th March 2020)

• Record Type: Journal Article
• Authors: Murugesan, M.; Mori, K.; Bea, J.C.; Koyanagi, M.; Fukushima, T.
• Is Part Of: Japanese journal of applied physics. Volume 59:Number SG(2020)
• Publication Date: 2020-03-04
• Subjects: Electroless plating -- Ni barrier/seed layer -- sub-micron Ni/Cu-TSV -- interposer Cu-TSV; Physics -- Periodicals; 621.05
• DOI: 10.35848/1347-4065/ab75b8
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: A feasibility study has been carried out to find an alternative method to the laborious cum expensive physical vapor deposition (PVD)/atomic layer deposition for the deposition of barrier and seed metal layers inside the deep Si trenches with aspect ratio (AR) greater than 10, by using low-cost, highly-scalable, CMOS-compatible electroless (EL) plating method to plate Ni as (barrier cum) seed layer for the fabrication of sub- μ m as well as 10 μ m width copper through-silicon-vias (Cu-TSVs). Micro-structural data revealed that both sub- μ m and 10 μ m width TSVs with AR ranging from 12 to 17 were completely filled with Cu by using EL-Ni as a seed layer. Further, both scanning electron microscope and energy dispersive X-ray analyzes data confirms the conformal formation of EL-Ni all through TSV sidewall and TSV bottom, which is otherwise difficult to realize by the even sophisticated PVD tool. Therefore, the EL plating method appears to be a highly promising method for the conformal formation of barrier/seed layers inside the high AR TSVs for future three-dimensional integration and packaging applications.