Network architecture for a topological quantum computer in silicon. (14th January 2019)

• Record Type: Journal Article
• Authors: Buonacorsi, Brandon; Cai, Zhenyu; Ramirez, Eduardo B; Willick, Kyle S; Walker, Sean M; Li, Jiahao; Shaw, Benjamin D; Xu, Xiaosi; Benjamin, Simon C; Baugh, Jonathan
• Is Part Of: Quantum science and technology. Volume 4:Number 2(2019)
• Publication Date: 2019-01-14
• Subjects: quantum computing -- quantum dots -- spin qubits -- surface code -- silicon -- electron shuttling; Quantum theory -- Periodicals; Quantum theory; Periodicals; 530
• DOI: 10.1088/2058-9565/aaf3c4
• Languages: English
• ISSNs: 2058-9565

Abstract

Abstract: A design for a large-scale surface code quantum processor based on a node/network approach is introduced for semiconductor quantum dot spin qubits. The minimal node contains only seven quantum dots, and nodes are separated on the micron scale, creating useful space for wiring interconnects and integration of conventional transistor circuits. Entanglement is distributed between neighbouring nodes by loading spin singlets locally and then shuttling one member of the pair through a linear array of empty dots. A node contains one data qubit, two ancilla qubits, and additional dots to facilitate electron shuttling and measurement of the ancillas. A four-node GHZ state is realized by sharing three internode singlets followed by local gate operations and ancilla measurements. Further local operations produce an X or Z stabilizer on the four data qubits, which is the fundamental operation of the surface code. Electron shuttling is simulated in the single-valley case using a simple gate electrode geometry without explicit barrier gates, and demonstrates that adiabatic transport is possible on timescales that do not present a speed bottleneck to the processor. An important shuttling error in a clean system is uncontrolled phase rotation of the spin due to modulation of the electronic g -factor during transport, owing to the Stark effect. This error can be reduced by appropriate electrostatic tuning of the stationary electron's g -factor. While these simulations are unrealistic in neglecting spin–orbit, valley and decoherence effects, they are realistic with respect to the gate-induced potential landscape and are a first step towards more realistic modelling. Using reasonable noise models, we estimate error thresholds with respect to single and two-qubit gate fidelities as well as singlet dephasing errors during shuttling. A twirling protocol transforms the non-Pauli noise associated with exchange gate operations into Pauli noise, making it possible to use the Gottesman–Knill theorem to efficiently simulate large codes.