Trapped charge modulation at the MoS2/SiO2 interface by a lateral electric field in MoS2 field-effect transistors. Issue 1 (28th January 2019)

• Record Type: Journal Article
• Authors: Pak, Jinsu; Cho, Kyungjune; Kim, Jae-Keun; Jang, Yeonsik; Shin, Jiwon; Kim, Jaeyoung; Seo, Junseok; Chung, Seungjun; Lee, Takhee
• Is Part Of: Nano futures. Volume 3:Issue 1(2019)
• Publication Date: 2019-01-28
• Subjects: high electric fields -- MoS2 -- field-effect transistors -- charge trapping; Nanoscience -- Periodicals; 620.5
• DOI: 10.1088/2399-1984/aafc3a
• Languages: English
• ISSNs: 2399-1984

Abstract

Abstract: Controlling trapped charges at the interface between a two-dimensional (2D) material and SiO2 is crucial for the stable electrical characteristics in field-effect transistors (FETs). Typically, gate-source bias has been used to modulate the charge trapping process with a narrow dielectric layer with a high gate electric field. Here, we observed that charge trapping can also be affected by the lateral drain-source voltage ( V DS ) in the FET structure, as well as by the gate-source bias. Through multiple V DS sweeps with increasing measurement ranges of the V DS, we demonstrated that the charge trapping process could be modulated by the range of the applied lateral electric field. Moreover, we inserted a hexagonal boron nitride (h-BN) layer between the MoS2 and SiO2 layer to explore the charge trapping behavior when a better interface is formed. This study provides a deeper understanding of controlling the electrical characteristics with interface-trapped carriers and lateral electrical fields in 2D material-based transistors.