A low-complexity design for the terminal device of the urban IoT-oriented heterogeneous network with ultra-high-speed OFDM processing. (October 2020) - Yin, Xiuwen; Liu, Jianqi; Cheng, Xiaochun; Zeng, Bi; Xiong, Xiaoming
Highlights: An architecture of combining system-level design with circuit-level design. The cache-centric OFDM baseband structures based on memory mapping. A serialized FFT structure with very low complexity. Abstract: The heterogeneous network structure has great potential in improving the efficiency of data services in the IoT/VANET by exploiting its advantage of various resources. However, supporting multiple communication resources in the heterogeneous network (HetNET) often significantly increases the complexity of the terminal device, which is still a hurdle to the popularity of the HetNET scheme. In this paper, we propose a comprehensive approach of combining system-level design with circuit-level design to greatly reduce the hardware complexity of the terminal device of the HetNET scheme with ultra-high-speed orthogonal frequency division multiplex (OFDM) processing. A system-level on-board architecture based on system memory sharing and the novel cache-based baseband structures for the OFDM receiver and transmitter are designed respectively. In addition, a new serialized 128-point fast Fourier transform (FFT) structure is proposed. By inserting the shared cache into the baseband structure to separate the FFT processing from other data processing in the baseband, the proposed scheme can alleviate the strict constraint on the FFT throughput, which has the potential to greatly reduce the hardware complexity of the baseband. Moreover, this advantage will become more obvious in the future as the rapid increasing of system resources in the terminal devices in recent years. The evaluation results show the proposed scheme has a significant lower hardware complexity than the traditional solutions of pure circuit design.