A 10-bit SAR ADC using novel LSB-first successive approximation for reduced bitcycles. (September 2020) - Wang, Ling; Zhang, Chenggao; Wang, Jingyu; Ma, Rui; Zhu, Zhangming
Abstract: This paper presents a 10-bit ultra-low power least-significant bit first (LSB-first) successive approximation register analog-to-digital converter used in wearable electrocardiogram monitoring. Compared with the exsiting ones, the number of bitcycles taken in the proposed LSB-first scheme only relates to the difference between two adjacent samples and the capacitor array is reduced by 50%. Fabricated in 65 ​nm CMOS technology within a bio-sensor front-end circuit, the proposed LSB-first SAR ADC occupies an active area of 200 ​× ​450 ​μm 2, consumes 60.8 ​nW ​at 10 ​kHz sampling rate, and achieves 58.4 ​dB SNDR.