A PNP-triggered dynamic substrate GGNMOS with improved performances. (September 2020) - Sun, K.M.; Li, T.; Meng, L.Y.
Highlights: A PNP-triggered dynamic substrate GGNMOS for on-chip ESD protection was proposed and verified. The proposed device employed substrate current trigger technique and dynamic substrate technique. The characteristics of proposed device are investigated by TLP and vf-TLP test. The proposed device has overall improved ESD protection performances. Abstract: A novel PNP-triggered dynamic substrate GGNMOS (gate-grounded NMOS) structure is proposed and verified in 0.18 μm salicided CMOS process. Owing to the dynamic substrate technique and imbedded PNP transistor which injects triggering current to the substrate under ESD (electrostatic discharge) events, the proposed structure features a small trigger voltage, a small snapback region, a high robustness, and a larger margin of ESD design window is achieved. Compared with traditional dynamic substrate GGNMOS, the proposed structure promotes FOM (figure of merit) by 60%. So it is a more feasible solution in ESD protections applications of low-voltage and thin gate oxide process for its overall improved performances.