A novel approach to design a digital clock triggered modified pulse latch for 16-bit shift register. (19th August 2020)

• Record Type: Journal Article
• Authors: Pattanaik, Suraj
• Is Part Of: International journal of intelligent defence support systems. Volume 6:Number 1(2020)
• Page Start: 21
• Page End: 34
• Publication Date: 2020-08-19
• Subjects: low power -- clock pulse generator -- CPG -- inverted-inverter -- 180 nm -- Cadence Virtuoso -- complimentary pass transistor logic -- area-efficiency -- shift register; Artificial intelligence -- Military applications -- Periodicals; Cybernetics -- Periodicals; Experimental design -- Periodicals; 623.028563
• Languages: English
• ISSNs: 1755-1587

Abstract

A low power area reduced clock pulse generator and a modified clock sense pulse latch is proposed for conventional shift register. The proposed clock pulse generator basically based on the inverted inverter delay circuit and a pass transistor logic AND gate circuit. This clock pulse generator and modified clock sense pulse latch consumes low power and low area than other conventional clock pulse generator. Here the clock pulse generator consist of five number of back to back cascaded clock pulse circuit. The pulse generated from the proposed clock pulse generator helps to increase the speed, reduces the area and power of conventional shift register. The clock pulse generator and the modified clock sense pulse latch is designed and tested by the Cadence Virtuoso 180 nm technology. The power consumption for 16-bit shift register is 0.705 mW at 500 MHz clock frequency and 0.395 mW at 100 MHz frequency. The proposed shift register saved 12% area and 19.50% power rather than other conventional shift register.