Optimised memory allocation for less false abortion and better performance in hardware transactional memory. Issue 4 (3rd July 2020)

• Record Type: Journal Article
• Authors: Li, Xiuhong; Gulila, Altenbek
• Is Part Of: International journal of parallel, emergent and distributed systems. Volume 35:Issue 4(2020)
• Page Start: 483
• Page End: 491
• Publication Date: 2020-07-03
• Subjects: False abortion -- hardware transactional memory -- memory allocator -- cache line; Parallel computers -- Periodicals; Electronic data processing -- Distributed processing -- Periodicals; Computer algorithms -- Periodicals; 004.35
• DOI: 10.1080/17445760.2019.1605605
• Languages: English
• ISSNs: 1744-5760

Abstract

ABSTRACT: This paper introduces and tackles a special performance hazard in Hardware Transactional Memory (HTM): false abortion. False abortion causes many unnecessary transaction abortions in HTM and can greatly impact the performance, making HTM not that useful when it is adopted as a fast path for Software Transactional Memory. By introducing a new memory allocator design, we are able to put objects that are likely to be accessed together from different threads into different cache lines and thus avoid conflicts of hardware transactions in different threads. Experiments show that our method can reduce 47% of transaction abortion and achieve a speedup of up to 1.67× (averagely 22%), yet only consume 14% more memory, showing great potential to enhance current HTM technology.