A 4:1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology. Issue 4 (2nd April 2020)

• Record Type: Journal Article
• Authors: Garg, Sandeep; Gupta, Tarun K.; Pandey, Amit K.
• Is Part Of: International journal of electronics. Volume 107:Issue 4(2020)
• Page Start: 513
• Page End: 541
• Publication Date: 2020-04-02
• Subjects: Dynamic -- VLSI -- CNTFET -- FOM -- CMOS; Electronics -- Periodicals; Electronic control -- Periodicals; 621.381
• DOI: 10.1080/00207217.2019.1663942
• Languages: English
• ISSNs: 0020-7217

Abstract

ABSTRACT: This paper proposes a 4:1 Multiplexer (MUX) designed using proposed Dual Chirality High-Speed Noise Immune Domino Logic (DCHSNIDL) technique for designing lower delay noise immune domino logic circuits in Carbon Nanotube Field Effect Transistors (CNTFETs) technology. Dynamic power consumption, speed and noise immunity of the circuit are improved by changing the threshold voltage of the CNTFETs. The chirality indices of the carbon nanotubes (CNTs) are varied to change the threshold voltage of the CNTFETs. Simulations are carried out for 32 nm Stanford CNTFET model in HSPICE for 2-, 4-, 8- and 16-input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9V. The proposed DCHSNIDL domino circuit reduces power consumption by a maximum of 61.77% and propagation delay by a maximum of 55.11% compared to Current-Mirror Based Process Variation Tolerant (CPVT) circuit in CNTFET technology. The proposed CNTFET-based domino technique shows a maximum reduction of 96.31% in power consumption compared to its equivalent circuit in CMOS technology for a 4-input OR gate. The proposed technique shows an improvement of 1.04× to 1.35× times in Unity Noise Gain (UNG) compared to various existing techniques in CNTFET technology. The 4:1 MUX designed using proposed technique has 48.91% lower propagation delay and consumes 52.80% lower power compared to MUX using CPVT technique.