An efficient hardware implementation of the elliptic curve cryptographic processor over prime field, Fp. (1st March 2020)

• Record Type: Journal Article
• Authors: Kudithi, Thirumalesu; R, Sakthivel
• Is Part Of: International journal of circuit theory and applications. Volume 48:Number 8(2020)
• Page Start: 1256
• Page End: 1273
• Publication Date: 2020-03-01
• Subjects: application‐specific integrated circuits (ASICs) -- elliptic curve cryptography (ECC) -- elliptic curve point multiplication -- field‐programmable gate arrays (FPGAs) -- modular arithmetic unit -- public‐key cryptography (PKC); Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2759
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: Elliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest‐Shamir‐Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, F p . This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex‐7 FPGA platform over 224‐bit and 256‐bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal‐oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field F 224 and F 256, respectively. This design provides better area‐delay product and high throughput value in both FPGA and ASIC when compared with other designs. Abstract : This paper proposes a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, Fp. This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources. This design provides better area‐delay product and high throughput value in both FPGA and ASIC when compared with other designs.