Low EOT and oxide traps for p-substrate Ge MOS device with hafnium nitride interfacial layer. (September 2020)

• Record Type: Journal Article
• Authors: Ruan, Dun-Bao; Chang-Liao, Kuei-Shu; Hsu, Wen-Yen; Yi, Shih-Han; Lee, Yao-Jen
• Is Part Of: Vacuum. Volume 179(2020)
• Publication Date: 2020-09
• Subjects: Ge MOS device -- Interfacial layer -- Hafnium nitride -- Equivalent oxide thickness -- Oxide traps; Vacuum -- Periodicals; 621.55
• DOI: 10.1016/j.vacuum.2020.109479
• Languages: English
• ISSNs: 0042-207X

Abstract

Abstract: Effects of interfacial layer on p-substrate germanium (pGe) metal oxide semiconductor (MOS) device were studied in this work. Although excellent characteristics in n-substrate Ge MOS device were reported, pGe MOS device often suffers a poor interface quality and large gate leakage current, while the equivalent oxide thickness (EOT) is scaled down below 1 nm. A novel hafnium nitride (HfN) interfacial layer (IL) is proposed to replace the traditional germanium dioxide thanks to its good thermal stability. As a result, the pGe MOS device with HfN IL exhibits a low EOT of 0.58 nm, a low leakage current density of 2.4 × 10 −4 A/cm 2, a lower hysteresis value of 150 mV, a better frequency dispersion, and lower oxide/border traps. Therefore, HfN is a promising IL to achieve high performance pGe MOS device. Highlights: Effects of interfacial layer on p-substrate Ge metal oxide semiconductor device were studied. A novel hafnium nitride (HfN) interfacial layer (IL) is proposed thanks to its good thermal stability. pGe MOS device with HfN IL exhibits lower EOT, leakage current, hysteresis, and oxide traps. HfN is a promising IL to achieve high performance pGe MOS device.