Vanishing Hysteresis in Carbon Nanotube Transistors Embedded in Boron Nitride/Polytetrafluoroethylene Heterolayers. Issue 8 (16th June 2020)

• Record Type: Journal Article
• Authors: Kumar, Sandeep; Dagli, Daghan; Dehm, Simone; Das, Chittaranjan; Wei, Li; Chen, Yuan; Hennrich, Frank; Krupke, Ralph
• Is Part Of: Physica status solidi. Volume 14:Issue 8(2020)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2020-06-16
• Subjects: boron nitride -- carbon nanotubes -- hysteresis -- polytetrafluoroethylene -- transistors; Solid state physics -- Periodicals; 530.4105
• DOI: 10.1002/pssr.202000193
• Languages: English
• ISSNs: 1862-6254

Abstract

Abstract : Carbon nanotube field‐effect transistors fabricated on silicon wafers with thermal oxide often suffer from large gate‐voltage hysteresis, induced by charge trapping sites in oxides, surface hydroxyl groups, and the presence of water molecules. Surface functionalization and passivation, as well as vacuum annealing and reduced operating temperature, have shown to diminish or even eliminate hysteresis. Herein, the fabrication of nearly hysteresis‐free transistors on Si/SiO2 by embedding carbon nanotubes and the connecting electrodes in a hexagonal boron nitride (h‐BN) bottom layer and a polytetrafluoroethylene (PTFE) top layer is demonstrated. The conditions at which catalyst‐free synthesis of h‐BN on SiO2 /Si with borazine is obtained, and the subsequent liquid‐phase deposition of PTFE, are discussed. Device transfer curves are measured before and after PTFE deposition. It is found that the hysteresis is reduced after PTFE deposition, but vanishes only after a waiting period of several days. Simultaneously, the on‐state current increases with time. The results give evidence for the absence of trap states in h‐BN/PTFE heterolayers and a high breakthrough field strength in those wafer‐scalable materials. Abstract : Fabrication of hysteresis‐free carbon nanotube devices on silicon wafers remains challenging for nanotubes deposited on top of electrodes. Herein, a wafer‐scalable process that yields nearly hysteresis‐free carbon nanotube transistors by assembling the devices between a hexagonal boron nitride (h‐BN) bottom layer grown on Si/SiO2 and a Teflon top layer is introduced.