An improved current mode logic latch for high‐speed applications. (29th July 2019)

• Record Type: Journal Article
• Authors: Kumawat, Mahesh; Upadhyay, Abhishek Kumar; Sharma, Sanjay; Kumar, Ravi; Singh, Gaurav; Vishvakarma, Santosh Kumar
• Other Names: Krishna P. Venkata guestEditor.; Yenduri Sumanth guestEditor.; Ariwa Ezendu guestEditor.
• Is Part Of: International journal of communication systems. Volume 33:Number 13(2020)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2019-07-29
• Subjects: current mode logic -- frequency divider -- high‐speed latches; Telecommunication systems -- Periodicals; 621.382
• DOI: 10.1002/dac.4118
• Languages: English
• ISSNs: 1074-5351

Abstract

Summary: In this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology. Abstract : In this paper, an improved current mode logic (CML) latch design for high‐speed on‐chip applications is proposed. The current mode logic latch is the key element for designing of transceivers in wireless/wire‐line applications, and this low‐power CML latch results in high output frequency application of 16 GHz. The delay model is also developed based on small signal equivalent circuit using 180‐nm standard CMOS technology.