Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing. (August 2020)

• Record Type: Journal Article
• Authors: Hossain, MD Shazzad; Savidis, Ioannis
• Is Part Of: Microelectronics journal. Volume 102(2020)
• Publication Date: 2020-08
• Subjects: Near-threshold computing -- Low power circuits -- Dynamic differential signaling based logic -- Current mode logic -- Robustness to noise and variation; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104801
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, novel circuit topologies for near-threshold computing (NTC) are proposed and evaluated. Three separate dynamic differential signaling based logic (DDSL) families are developed in a 130 nm technology to operate at 400 mV and 450 mV. The proposed logic families outperform contemporary CMOS and current-mode logic (CML) circuits implemented for near-threshold. The DDSL families are described as dynamic current-mode logic (DCML), latched DCML (LDCML), and dynamic feedback current-mode logic (DFCML). Simulation and analysis are performed through implementation of boolean functions and a 4×4 bit array multiplier. At a 450 mV supply voltage, the total power of the 4×4 DFCML multiplier is reduced to 0.95× and 0.009×, while the maximum operating frequency is improved by 1.4× and 1.12× as compared to, respectively, a CMOS and CML multiplier. The DCML multiplier consumes 1.48× the power while improving f max by 1.65× as compared to a CMOS multiplier. A chain of four inverters implemented with the developed dynamic logic families exhibited an energy delay product (EDP) of 0.27× and 0.016× that of, respectively, CMOS and CML implementations. The mean noise margins, also evaluated with a chain of inverters, of DFCML and LDCML are at least 2.5× greater than that of CMOS.