0.7-V supply, 21-nW All–MOS voltage reference using a MOS-Only current-driven reference core in digital CMOS. (August 2020)

• Record Type: Journal Article
• Authors: Aminzadeh, Hamed; Valinezhad, Mohammad Mahdi
• Is Part Of: Microelectronics journal. Volume 102(2020)
• Publication Date: 2020-08
• Subjects: Line regulation -- Low power -- MOS-Only -- Resistorless -- Temperature compensation -- And voltage reference; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104841
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A nano-power all-MOS voltage reference circuit is proposed without any integrated resistor or bipolar transistor to generate multiple voltage sources in inexpensive digital CMOS technologies. The design is based on a current-driven voltage reference core made by standard nMOS transistors only, and can be powered up by a flexible biasing current with no consideration on its temperature characteristics. The sensitive core is shielded from the unregulated voltage supply via a voltage follower MOS transistor, whose gate terminal is driven by a supply-insensitive voltage source coming from the internal biasing configuration. The additional voltage reference is generated using the type of the biasing current made by the main voltage reference loaded by a transistor. A MOS-only implementation of the proposed reference employs MOS devices instead of passive resistors and linear capacitors. A prototype of the proposed solution consumes 30 ​nA with an area of 0.01 ​mm 2 in 0.18-μm CMOS process, producing a main voltage reference of 147 ​mV while operating at the supply voltage down to 0.7 ​V. Simulation results demonstrate an average temperature coefficient (TC) of 66.38 ​ppm/ ° C for a temperature range of −40 to 120 ​°C. The line sensitivity is about 0.031%/V for the line voltages above 1.3 ​V. The mean power supply rejection ratio (PSRR) is −90 dB and −64.4 ​dB ​at 10 ​Hz and 1 ​MHz, respectively, when the voltage supply is set to 1.8 ​V and an equivalent MOS capacitor of 5 ​pF is used at the output. The 1% start-up settling time is 240 μs for a 1.0 ​V voltage supply step, and can be reduced by increasing the supply voltage magnitude.