A 30Gbps power-efficient dual-loop adaptive equalizer in 0.13 ​ ​μm SiGe BiCMOS technology. (June 2020) - Li, Jiquan; Chen, Yingmei; Chen, Lufeng; Guo, Chao
Abstract: A 30Gbps power-efficient equalizer including an adaptive loop combined with a direct current offset cancellation (DCOC) loop is presented in this paper. Based on spectrum balanced technique, the adaptive loop applies signal strength indication (SSI) circuit to detect the low and high frequency power of equalized signal. After that, peaking gain of equalizer is adjusted according to detection value of SSI circuits. With the help of operation amplifier and trans-conductance amplifier, the proposed DCOC loop decreases the mismatch error. By applying inductive peaking and RC-degeneration technique, the continuous time linear equalizer (CTLE) compensates for channel insert loss in equalizer. A double- f T cell with inductive peaking technique is utilized to expand the bandwidth. To reduce effect of parasitic capacitor from output buffer, equalized signal is reshaped by three-stage cascaded limiting amplifier. Benefiting from excellent impedance matching by employing micro-strip and peaking inductor in terminal, the maximum channel loss equalized at 14 ​GHz is −18dB. The maximum reflection loss of Sdd11 and Sdd22 measured at 42 ​GHz and below are -9dB. Peak-peak jitter of 11.33ps is measured at 30Gbps after equalization. Meanwhile, only 53 ​mW power dissipation is consumed with a power supply of 1.8 ​V. Fabricated in 0.13 ​ ​μm SiGe BiCMOS technology, this chip only occupies active area of 0.32 ​mm 2 .